1. Field of the Invention
The present invention relates to nonvolatile semiconductor memory and to a data writing method for nonvolatile semiconductor memory.
2. Description of the Related Art
Nonvolatile semiconductor memory is known that has two charge accumulation sections in a single memory cell, and two bits of storage capacity for each memory cell by storing two values (“0” and “1”) in the charge accumulation sections. Such a memory cell has an nMOSFET structure, for example, and has two charge accumulation sections that are formed at a distance from each other at the drain side and the source side. A state in which a charge is accumulated in the charge accumulation sections corresponds to “0” data, for example, and a state in which a charge is not accumulated corresponds to “1” data, for example, whereby two bits of data can be stored per memory cell, one bit in each charge accumulation section. The data of this memory cell are written, read, and erased by the method described below, for example.
For example, in the case of writing the data “0” to the charge accumulation section on the drain side, a positive voltage is applied to the drain terminal and the gate terminal, and the ground voltage is applied to the source terminal. Hot electrons are thereby injected to the charge accumulation section on the drain side and retained, and the data “0” is written.
When the data stored in the charge accumulation section on the drain side is read, a positive voltage is applied to the source terminal and the gate terminal, and the ground voltage is applied to the drain terminal. When a charge is not accumulated in the charge accumulation section on the drain side at this time, i.e., when the data “1” is stored in the drain-side charge accumulation region, a comparatively large read current is obtained. On the other hand, when a charge is accumulated in the charge accumulation section on the drain side, i.e., when the data “0” is stored in the drain-side charge accumulation section, the effects of the accumulated charge make the read current lower than when the data “1” is stored. Since the amount of the read current thus differs according to the presence of a charge in the charge accumulation section, data can be read by determining the amount of the read current.
In the case of erasing the data stored in the charge accumulation section on the drain side, a positive voltage is applied to the drain terminal, a zero voltage or negative voltage is applied to the gate terminal, and the source terminal is placed in an open state. Hot holes that occur in the vicinity of the drain region are thereby injected to the charge accumulation section, and the charge accumulated in the charge accumulation section is neutralized, whereby the data is erased.
FIG. 1 is a graph showing an ideal distribution of the read current in the memory cell having two bits of storage capacity (hereinafter referred to as 2-bit memory cell), wherein the horizontal axis indicates the read current value, and the vertical axis indicates the frequency. As shown by the graph, the read current is distributed at a certain width about a corresponding reference value for each data element “0” and “1”. The range between the read current distributions that correspond to the mutually different data (“0” and “1”) is referred to as the current window. An adequately wide current window must be ensured in order to accurately read the data written in the memory cell. In other words, the data becomes difficult to accurately read when the read current value for the data “0” and the read current value for the data “1” are close to each other.
Nonvolatile semiconductor memory has recently been developed that has two charge accumulation sections in one memory cell, and four bits of storage capacity per memory cell by storing four values of data (“00”, “01”, “10”, “11”) in the charge accumulation sections. Four-value (i.e., 2-bit) data storage in the charge accumulation sections is accomplished by also controlling the amount of charge accumulated in the charge accumulation sections and associating the amounts of accumulated charge to each of the four values of data. The data are read according to the same principle as the 2-bit memory cell described above, and the four values of data are determined by reading the value of the read current.
In the case of a 4-bit memory cell, the current window is narrower than in the case of the 2-bit memory cell shown in FIG. 1. In other words, in comparison to the 2-bit memory cell in which only the presence of a charge is determined, higher read precision is required in a 4-bit memory cell, which the amount of the accumulated charge must also be determined.
Furthermore, a semiconductor memory cell having two charge accumulation sections in a single memory cell has problems in that the read current of the data written in one of the charge accumulation sections is reduced by writing to the other charge accumulation section of the same memory cell. Specifically, the value of the read current that corresponds to the data “1” is reduced by a subsequent writing of the data “0” to the other charge accumulation section. The reason for this is considered to be that the flow of the read current for the data “1” stored in one charge accumulation is impeded by the charge that is accumulated in order for the data “0” to be stored in the other charge accumulation section. After writing of data to one charge accumulation section is completed, data is written to the other (mirror side) charge accumulation section in the same memory cell, whereby the read current that would have been obtained in accordance with the data written to the one charge accumulation section decreases subsequently. The current window then decreases in width, which leads to reduced accuracy of data reading.
In a 2-bit memory cell, a measure referred to as verify writing is adopted whereby such a reduction in the read current of the mirror side is taken into account, data write processing is performed incrementally over a plurality of cycles so as to minimize the amount of current reduction, and the write processing is ended once the read current has reached a predetermined target value that is in accordance with the stored data. Specifically, verify writing is a data writing method for injecting current in incremental steps so as to obtain the desired read current by alternately injecting current to the charge accumulation section and verifying the read current repeatedly. Through this verify writing, fluctuation of the read current can be suppressed for a plurality of memory cells, and reductions in the read current of the mirror side by excessive charge accumulation can be kept to a minimum in comparison to a case in which the entire charge is injected at once.
However, since the current window of a 4-bit memory cell is narrower than the current window of a 2-bit memory cell, as described above, the abovementioned problem of reduced read current on the mirror side cannot be overcome merely by verify writing.
Japanese Laid-open Patent Publication No. 2008-85196 proposes the data writing method described below for overcoming the abovementioned problem of current reduction on the mirror side in a nonvolatile semiconductor memory in which a plurality of 4-bit memory cells is arranged in an array and capable of storing two bits of data in each of two charge accumulation sections formed on the source side and the drain side.
The four bits of data to be stored in each memory cell are divided into two higher bits and two lower bits. Of the 2-bit data divided for the plurality of memory cells, the data “00”, for which the read current is the lowest (i.e., the charge accumulation amount is the greatest) are all stored first. Specifically, the data “00” are written first among the data divided in the charge accumulation sections of the source side and drain side of each memory cell. After storage of the data “00” is completed for the charge accumulation sections, the other data “01” and “10” are written. Since a state in which a charge is not retained in a charge accumulation section corresponds to the data “11,” there is no need for specific write processing when the data “11” is stored. Writing of each data element is differentiated by varying a gate voltage Vgw in accordance with the stored data, the gate voltage Vgw being fed via a word line, and the drain-source voltage Vdsw is constant regardless of the value of the stored data. During writing of the data, charge injection and write current verification are performed in alternating fashion, and writing is completed once the write current has reached a predetermined value. When the data “01” and “10” are written, the number of writes is coordinated.
By this type of data writing method, since the data “00” having the lowest read current is written first, it is possible to prevent the read currents of the data “01” and “10” subsequently written to the other charge accumulation section of the same memory cell from subsequently fluctuating. Although the read current of the data “00” is reduced by the data “01” and “10” subsequently written to the other charge accumulation section of the same memory cell, since the data “00” has the lowest read current of the four values of data, the current window is not narrowed, and no problems therefore occur. For the data “01” and “10,” since charges are injected incrementally over a plurality of cycles while the read current is verified, fluctuation of the read current between cells can be minimized, and the current window can be ensured.